Integrated circuit (IC) devices are formed in multiples on semiconductor wafers and then diced into individual IC devices. The IC devices generally have rectilinear shapes and are formed in a matrix array on semiconductor wafers. Once the formation of IC devices are completed, the semiconductor wafers are diced into individual IC devices. The dicing operation involves scribing between the rows and columns of the IC devices on the semiconductor wafers using a dicing saw. The area between the IC devices that get scribed are called scribe lines.
The scribing is carried out on the active side of the semiconductor wafers where the integrated circuits and the multi-layer wiring layers of the IC devices are formed and the scribe lines are defined in the areas of the wafer between each individual IC devices (die patterns). The scribe line areas do not have circuit elements of the die areas and because each die is an independent device, the metal features for interconnect wiring conductors are also confined to the die areas and do not extend into or across the scribe lines where the die saw will cut through the wiring layers. However, some wafer-level reliability and functionality test pads are located in the scribe line areas to facilitate wafer-level testing. In such wafers, the die sawing across the test pads generally results in severe dielectric peeling and cracking. These delaminations easily become sources of defects that detrimentally affect reliability of the diced chips.
In semiconductor wafers for advanced 45 nm dimension IC devices, the lower level wiring layers, also known as IMD layers, use ELK dielectric materials as the insulator material between the wiring conductor features. An example of an ELK dielectric material is a trimethylsilane-based organosilicate glass with a dielectric constant as low as about 2.1. In these wafers, one or more top-level wiring layers above the ELK layers are formed of undoped silicate glass (USG) as the insulator material between the wiring conductor features. In these wafers, the interface between the ELK layers and the USG layers suffer high level of delamination at the corner areas during scribing of the scribe lines by the dicing saw, regardless of whether there are metal features in the corner areas. The delamination is believed to be caused by high level of residual stress at the ELK/USG interface attributed to the substantial difference in the coefficient of thermal expansion (CTE) and Young's modulus between the ELK and the USG insulators. The CTE and Young's modulus of the ELK material is substantially different from those of the USG. The typical CTE and Young's modulus of ELK dielectric is about 0.7 ppm/° C. and 10 GPa, respectively. The typical CTE and Young's modulus of USG material is about 0.5 ppm/° C. and 70 GPa.
The peeling defects cause reliability problems with the IC devices and are not desired. Thus, there is a need for improved scribe line structures especially for IC devices utilizing ELK dielectric for IMD layers and USG dielectric for top-level wiring layers.